1. Field of the Invention
The present invention generally relates to clocking systems for electronic circuits, and more particularly to a method of generating clocking signals for audio components in an electronic video device.
2. Description of the Related Art
Various types of electronic circuits have been constructed that support a wide range of different clock modes. For example, digital data converters used in audio and video devices (players or recorders) can operate in different speed modes wherein different master clock rates and sample clock rates are used. A digital-to-analog converter in such a device might have two operating modes, such as a base mode and a high mode, depending on what master clock rate and sample clock rate are being provided from the front-end circuitry. This capability allows a single converter to support multiple applications, and gives the end-user (i.e., the final product manufacturer) greater flexibility in the design of the overall electronic system.
A typical clocking system for a conventional digital versatile disc (DVD) player 10 is illustrated in FIG. 1. A piezoelectric crystal 12 is used by an oscillator 14 to create a master clock signal which is fed to two phase-lock loops (PLLs) 16 and 18. In a typical video system, oscillator 14 provides a 27 megahertz (MHz) signal which facilitates clock generation for both U.S. and international video standards. Audio PLL 16 provides an audio clock signal for an audio processing unit 20, and optional video PLL 18 provides a video clock signal for a video processing unit 22. For high performance video systems, the video PLL may be used to multiply the clock to a higher frequency, such as 54 MHz for 108 MHz. An optical reader 24 reads the information optically recorded on the DVD and provides data signals to audio processing unit 20 and video processing unit 22. Audio processing unit 20 and video processing unit 22 provide various digital signal processing (DSP) functions, such as decompression of encoded audio and video data streams. The decompressed digital audio data stream is fed to a first digital-to-analog controller 26, and the decompressed digital video data stream is fed to a second digital-to-analog controller (DAC) 28. DAC 26 produces the audio output of DVD player 10, and DAC 28 produces the video output of DVD player 10. These outputs drive the audio and video output ports of DVD player 10 which allow interconnection to audio and video devices, i.e., speakers and a display.
DAC 26 is controlled by clock signals provided from audio PLL 16, and DAC 28 is controlled by clock signals provided from video PLL 18. For example, DAC 26 receives a master clock signal and a sample rate clock signal which are used to sample the digital audio data from audio processing unit 20 and generate the proper analog audio output. The master clock signal might be in the range of 8 MHz to 34 MHz, and the sample rate clock signal might be in the range of 32 kilohertz (kHz) to 192 kHz. The master clock is normally a multiple (such as 256) of the base sampling rate. In a typical digital-to-analog converter, a delta-sigma modulator feeds a multilevel noise-shaped signal based on the digital input stream to a back-end analog filter which removes high frequencies from the output. The clock signals from audio PLL 16 are used by internal components of DAC 26 such as the delta-sigma modulator and the analog filter. As the audio master clock, e.g. 44100*256 Hz, is not a simple rational multiplier of the master crystal oscillator, the quality of the clock typically suffers due to a low frequency of the lock signal and typical PLL noise issues. While it is possible to build clock generation systems that avoid this noise, most video systems have audio clocks with significant jitter and phase noise.
Data converters can be quite sensitive to clock noise and jitter. Jitter can move the effective sampling time of the signal, causing modulation sidebands and distortion. This situation is especially true for high-frequency, high-level signals. Additionally, the out-of-band modulation noise in delta-sigma structures can be de-modulated to become in-band noise signals. These effects degrade both dynamic range, and signal-to-noise ratio (SNR) measurements.
One problem that can arise in providing these critical timing signals to DAC 26 relates to the jitter associated with audio PLL 16. A phase-lock loop is a feedback device which includes a phase/frequency detector, a low-pass filter, and a voltage-controlled oscillator (VCO). The phase/frequency detector compares two input signals, a reference signal (from the external system clock, i.e., oscillator 14) and a feedback signal, and generates a phase error signal that is a measure of their phase difference. The phase error signal from the detector is filtered by the low-pass filter and fed into the control input of the VCO. The VCO generates a periodic signal with a frequency which is controlled by the filtered phase error signal. The VCO output is coupled to the feedback input of the phase/frequency detector, thereby forming a feedback loop. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the filtered phase error signal causes the VCO frequency to shift toward the frequency of the reference signal, until the VCO finally locks onto the frequency of the reference. The output of the VCO is then used as the synchronized signal.
Jitter can be introduced into the feedback loop due to the “dead zone.” The phase error signal that controls the VCO has a first polarity in the case where the reference signal has a phase lag, and the other polarity when a phase lead is detected. For very small phase differences (e.g., the zero-phase error, steady-state condition of the locked PLL), in the transition from one polarity to the other there is often a region referred to as the dead zone where the phase error signal is insensitive to phase-difference changes. In this dead zone (or dead band), the VCO's eventual output signal is unpredictable and liable to dither. Additionally, noise may be injected into the VCO from other circuitry that is above the corner frequency of the PLL feedback loop.
In light of the foregoing, it would be desirable to devise an improved method of providing clock signals to audio components of an electronic video device which could avoid the performance problems associated with PLL jitter. It would be further advantageous if the method could be implemented without significantly increasing hardware size.